A consortium of leading technology vendors has joined forces to develop new specifications for connecting accelerator hardware to processors, ensuring that processors with different architectures can share data seamlessly with accelerators and drive heterogeneous computing in the data centre.
The new Cache Coherent Interconnect for Accelerators (CCIX) specifications are being developed by a group comprising AMD, ARM, Huawei, IBM, Mellanox, Qualcomm and Xilinx in a bid to develop a standard way to connect accelerator hardware to processors.
Accelerators are becoming an increasingly common feature in data centre environments, as applications such as big data analytics, media processing and software-defined networking drive the need for key specific functions to be optimised in hardware, often by using field programmable gate arrays.
CCIX is intended to allow such components to access and process data irrespective of where it resides, and without the need for complex programming environments, to enable existing server ecosystems to benefit from accelerators.
The involvement of AMD, ARM and IBM, which ensures that CCIX works across x86, ARM and Power processor architectures, is clearly important, but scant detail is available from the website dedicated to the CCIX partnership.
Some light may be shed on the matter by the fact that IBM already has a technology known as Coherent Accelerator Processor Interface that enables a plug-in accelerator, such as a GPU sitting on the PCI Express bus, to operate as if it is an on-chip peer to the cores on a Power8 processor. This may have been the genesis for CCIX.
"IBM is committed to working with like-minded industry leaders to expand our efforts around open coherency to help meet our clients' growing cognitive needs," said Brad McCredie, IBM Fellow and vice president of Power development.
"CCIX enables greater performance and connectivity capabilities over existing interconnects, and paves the road to the next-generation CPU - accelerator - network standard interface."
Gilad Shainer, vice president of marketing at Mellanox, a firm that specialises in interconnectivity products and technologies, added: "With an anticipated broad ecosystem support of the CCIX standard, data centres will be able to optimise data use, thereby achieving world-leading applications efficiency and scale."
Meanwhile, AMD has long championed what it calls heterogeneous computing, whereby different processors can be used in a system to deliver optimal overall performance for specific applications. A case in point is the firm's own APU products, which combine CPU and GPU cores on the same chip.
"By joining with others in the industry to develop new interconnect specifications to accelerate performance, AMD continues its commitment to open, heterogeneous computing," said Gerry Talbot, corporate fellow and vice president of I/O and circuit technologies at AMD.
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