Intel has disclosed more details about its segmented roadmap and for the first time has shown a diagram of the Merced die.
Paul Otellini, executive vice president, Intel architecture business group, described the Celeron platform "fresh from the factory" and the "fighting brand".
Speaking at an Intel analysts? forum on Friday, he said the ramp was the fastest release of CPUs for Intel ever, with four times volume growth between Q2 and Q3 of this year.
He confirmed that a 400MHz part will appear in the first half of next year, along with integrated companion chipsets, and promised further integration in the year 2000.
Otellini claimed Java runs better on Intel?s architecture than on other platforms, and as proof cited Jmark 2.0 benchmarks, which he said showed a PII/300 running Win95/NT outperformed a 266MHz PowerPC G3 running MacOS 8, and a Sun 296MHz UltraSparc II running Solaris 2.6.
Next year, Otellini claimed, will see Intel ship 500MHz parts on the .25 micron process in the first six months, and 600MHz parts on .18 micron in the second half, with mobile parts using the .18 micron process ramping to volume in the third quarter of 1999.
An IA32 server roadmap he displayed showed Cascades arriving just before the end of next year, Foster in the first half of 2000, with future 32 products extending far into the first half of the decade.
Madison, Deerfield and McKinley are slated for the end of 2001, Otellini's roadmaps showed. Analysts also got a glimpse of the Merced floorplan, shown here.
In the first half of 1999, Intel will release Tanner 500MHz for the server market, Katmai 500MHz for the mainstream market, Celeron 400MHz for the budget mark, 366MHz mobile PIIs for the notebook market, and StrongARM 1100/1500 chips for the set top box and handheld market.
The second half will see 600MHz Cascades for the server market, Coppermine 600MHz for the mainstream market, Celerons at greater speeds than 400MHz for the budget market, a mobile PII Coppermine at 600MHz and StrongARM upgrades.
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