AMD's Dresden plant has started shipping samples of its x86 microprocessors using the copper interconnect process, according to chairman Jerry Sanders.
The company will produce the Thunderbird version of its Athlon using 0.18 micron copper technology, and later this year the technology will be migrated to a 0.13 process. Thunderbird will include cache on die, with chips shipping in June.
Copper is becoming more common because of its relatively low resistance compared with conventional aluminium interconnects. This makes a big difference in chip design, where faster interconnect speed can yield greater performance.
Intel is not currently using copper in its 0.18 micron process, but it is expected to introduce it with the 0.13 micron process by 2001.
Sanders would not reveal the speed of the new Athlon until it ships, but he claimed that AMD is seeing excellent speed results. "The process is going well and according to plan," he said.
Thunderbird is one of four processors AMD is slated to introduce this year. Sanders said AMD will introduce its Spitfire processor with on-chip cache by June, followed by its Mustang mobile processor with up to 2Mb of on-chip cache, as well as a low-end version in the fourth quarter (CRN, 5 April).
All of the chips will be compatible with AMD's new Slot A architecture.
Sanders said Spitfire and Thunderbird will be available in a PGA package, but only after Slot A ships.
By the end of 2001, AMD expects to introduce its 32bit and 64bit Sledgehammer processor, which will run at 2GHz speeds.
AMD has teamed up with security provider Wave Systems to incorporate Wave's Trusted Client security architecture into its commercial and consumer motherboards. The aim is to create an open industry standard that will lead to enhanced security for documents, as well as remote access and authenticated network log-on.
AMD and Wave both participate in the Trusted Computing Platform Alliance, which aims to develop hardware and software specifications to enhance platform security, and are looking to deliver the details of their developments to the standard's body by the second half of 2000.
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