Silicon technology is fast reaching the limits of atomic engineering, and the industry is going to need a revolution in design in the coming years, delegates at Semicon West 2010 have been told.
Bernard Meyerson, IBM's vice president of innovation, said during his keynote address that silicon is being engineered on such a small scale that a whole new way of building chips is needed.
For example, scientists have already been able to build 2.6nm carbon nanotubes that function as a transistor, but there is no way to manufacture them in the kind of bulk needed to be useful to the wider industry.
"Silicon doesn't scale to these dimensions," he said. "There's a challenge. The industry is up to it, but at what cost? That's the question."
The problems are too big and too expensive for any one company to handle, according to Meyerson.
The average return on $1 of R&D spending in the 1950s was in the region of $50, but this has fallen to $6 now because chips have become more complex.
Companies need therefore to collaborate or consolidate. There will be a lot of mergers in the years ahead, Meyerson said, but IBM is working on collaborative efforts between companies.
FinFET gating technology is an example of how this could work. AMD, IBM and Motorola had collaborated with academics to develop the double-gate transistor technology in a way that would have been too big a financial risk for one player.
Another area that needs addressing is chip proximity. Costs need to come down as optical networking grows, but chips have to be physically integrated to reduce latency.
"I never thought I'd say this, but the speed of light is woefully slow," Meyerson told delegates.
Another challenge is data analysis. Information is now being analysed in real time, and it is the companies that can build these kind of systems that will see the strongest growth in the future.
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