Scalability, high-bandwidth memory systems, cross-cluster instruction scheduling and execution were all topics of discussion at the 10th annual Hot Chips Symposium held in Silicon Valley this week.
Representatives from Compaq Computer, Sun Microsystems, IBM and Hewlett-Packard were among those describing new features of their respective chips.
The essence of this conference is to present to engineers real products, the organisers say, as opposed to something that only theoretically might get built.
Compaq, for example, pointed out its new 21264 Alpha chip has a 1gbps+ high bandwidth memory system.
"The 21264 proves that both high frequency and sophisticated architectural features such as six-way instruction issue and out-of-order execution, can co-exist," said Compaq's Rick Kessler.
Sun Microsystems' engineer Bill Lynch said the company's next generation 64-bit processor, the UltraSPARC III, executes 20 to 30 percent more quickly than its predecessor, the SPARC II.
He explained the processor scales with technology. In particular, on-chip memory controller and on-chip snoop tags scale system performance while increased clock rate and static speculation scales 64-bit application performance.
Hewlett Packard's David Johnson presented an overview of techniques for mitigating memory latency effects in the company's PA-8500 processor.
He pointed out that data fetching is a very effective technique and that included in the instruction fetch are features such as instruction cache and instruction prefetching.
Large caches, out-of-order queue as well as custom circuit designs or a combination of these are all mitigating memory latency effects, he added.
IBM spent some time outlining the advantages of its latets CMOS mainframe, the G5. Announced in May, the microprocessor design is based on previous generation G4 but with enhancements, the company said. Faster cycle time, new architectural features and improvements in reliability, availability and serviceability (RAS) were all touted.
Timothy Slegel, a co-author of IBM's design team, pointed out that scalability issue was addressed in IBM's 12 chip set design and in single issue in-order execution. The G5 doubles performance over any prior IBM mainframe.
"There is also a slow-mode when the processor detects exception conditions," he said.
In the embedded arena, Mitsubishi Electric's Toru Shimizu unveiled the company's M32Rx/D single chip microcontroller with a high capacity 4 MB internal DRAM and start-up Sandcraft introduced its first product the Genesis Microprocessor which provides 200+MHz, 400 Dhrystone MIPS, desktop performance.
Comcast's £29.7bn winning bid more than twice the £13.7bn Rupert Murdoch valued Sky at just eight years ago
A nuclear strike has been considered, but Bruce Willis is nowhere in sight
Spray-on antenna could enable seamless integration of antennas with everyday objects
Parker Solar Probe, TESS and GOLD missions will deliver exciting data, claims NASA