Intel expands chip instruction sets
Chip giant promises faster and more power-efficient computing
Intel is preparing to introduce a collection of 50 new chip instructions designed to make the handling of specific tasks more efficient, the company has revealed at the Intel Developer Forum in San Francisco.
"We are working with customers to understand the next evolution in the instruction set," said Pat Gelsinger, senior vice president at Intel's Digital Enterprise Group.
"What are their emerging workloads and how can we enhance the instruction of the platform to embrace those new usage models and deliver a solution that handles the data sets?"
The new instructions will target applications such as high performance computing, media processing and pattern recognition, Gelsinger said.
They form two groups: the Streaming SIMD Extensions 4 are designed to deliver increased performance and greater energy efficiency for most applications; and a set of Application Targeted Accelerators will provide low-latency, low-power fixed-function capabilities for targeted applications.
"All of these are new emerging workloads that the platform and the instruction set needs to comprehend," said Gelsinger.
The instruction set is a collection of commands that a processor understands and is able to execute.
Examples are the Intel Architecture 32, the Intel 64 which is used in 64-bit Xeon and Pentium processors and the Itanium processor's IA-64.
AMD has its own instruction sets such as the 64-bit x86-64, which is fully compatible with Intel 64.
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