Intel and Hewlett-Packard have pulled the covers off their Merced chip, giving developers their first clear technical details of IA-64's instruction set architecture.
A paper posted on the companies' Web sites last week contained details of the chip's instruction set and a programming model that would allow coders to take advantage of the processor's technology, called EPIC for explicitly parallel instruction computing.
EPIC technology requires far greater concentration on the programming and compilation of software, compared with traditional systems, but glean performance benefits from the new chip, so developers have eagerly anticipated these technical details.
Among the specifications unveiled are 128 integer registers, 128 floating-point registers and 64 predicate registers, as well as full support for MMX and SIMD.
The paper also covers Merced's compatibility with the current IA-32 and PA-RISC instruction sets.
While offering direct binary compatibility with IA-32, the new architecture can also offer compatibility with PA-RISC through software translation.
That is a procedure the chip uses to translate a PA-RISC instruction into a comparable IA-64 instruction.
Intel is expecting to ship sample quantities of Merced before the end of this year, with bulk quantities available in the second quarter of 2000.
The paper can be downloaded from www.hp.com/go/ia-64.
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