While MIPS Technologies drew attention to the message that programmable solutions can help get processors to market faster, rival UK chip designer ARM introduced a new processor core for high-end embedded devices at the Embedded Processor Forum 2002 this week in San Jose.
John Burgoin, chairman and chief executive at MIPS, told attendees during his keynote that design and wafer costs continue to be major challenges for chip designers.
"Programmability will be used to eliminate custom design wherever possible and getting to market a few months sooner can double, even triple profits," he said.
MIPS also revealed a new 32-bit core designed to optimise silicon on chip (SOC) designs implemented with multiple processor cores.
The company's MK4 multiprocessing core is the first to allow developers to insert user-defined instruction logic, which extends specific instructions for proprietary header-analysis tasks.
The M4K line is positioned between the uniprocessing 4K family on the low end and the enhanced uniprocessing 4KE series.
Emerging next to ARM and PowerPC architectures, the MIPS architecture has become known as one of the standard instruction sets in network processing.
"Multi-CPU SOCs are required to meet the high-bandwidth demands of advanced networking equipment," said Linley Gwennap, principal analyst at The Linley Group.
He explained that modern IC process technology easily supports many processors on a single chip but that the problem lies in connecting and debugging such complex designs.
ARM unveiled its ARM1026EJ-S processor core at the Forum which integrates its Jazelle Java-acceleration technology and runs at 325HMz when manufactured with a 0.13-micron process.
The company said that LSI Logic has become the first ARM semiconductor partner to license the new ARM1026EJ-S microprocessor core.
LSI plans to target advanced communications, storage and consumer applications with the new core.
ARM also released a new version of the ARM7TDMI core, which is manufactured on a 0.13-micron process and is used in mobile phones and other battery powered devices.
Motorola launched the low-end C-3e network processor and its companion Q-3 traffic management co-processor, which is designed for access equipment at the edge of the network and can process packets at a rate of 3Gbps.
Programmable network processors can process data traffic fast enough to keep up with a high-speed connection. They can also be upgraded through software to support new standards.
Bob Gohn, vice president of marketing for Motorola's network processors, said that the level of flexibility and performance of the C-3e would help deliver more services with faster time-to-market than was possible with standard products or ASIC-based designs.
"With the ability to mix and match network processors, traffic managers and adapters, customers can accommodate various system design requirements," he explained.
According to Gohn, the architecture of the chip allows makers of access routers and other devices to build in support for nearly any protocol they want to offer customers.
Eric Mantion, an analyst at MicroDesign Resources, maintained that Motorola continues to simplify the arduous job of designing the modern network.
"By providing programmable devices at almost every level of the communications hierarchy, network designers can create systems today with no fear of what tomorrow brings," he said.
According to Mantion, the C-3e NPU is particularly well thought out in that it provides flexibility in applications that are too small for a C-5e NPU but too big for a PowerQUICC II processor.
The use of reconfigurable processor cores was also a topic of discussion at the Forum.
Toshiba described a media processor architecture billed as "configurable and extensible", and STMicroelectronics talked of a face recognition processor based on the Xtensa core licensed from Tensilica.
Tensilica detailed new instruction extensions for MPEG-4 video decoding, while NEC described a low-power design for mobile multimedia terminals that can be tuned for video processing.
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