If the chip industry wants to keep doubling the performance of its processors every two years, it will need to start embracing Performance Systems on a Chip, according to The Semiconductor Industry Alliance (SIA).
The organisation made the claim on Monday, following the release of its international technology road map for semiconductors, which it claims is the first to draw on opinions from global sources.
Juri Matisoo, the SIA's vice president of technology, said the primary aim of the roadmap was to identify the technical challenges that vendors should focus their research and development efforts and funding on.
Two representatives each from Europe, Japan, South Korea, Taiwan and the US were sent to speak with 12 working groups on the subject and one of the key areas highlighted was traditional scaleability.
The SIA said that to further extend scaleability, vendors may need to introduce new materials into the basic CMOS structure of their chips to either replace or expand existing components.
Paolo Gargini, a fellow and technology strategist from Intel, explained: "It is expected that these new materials will provide a viable solution to extending the limit of the planar CMOS process for the next five to 50 years."
But even if these new materials were introduced, he added, it would be challenging to double the electrical performance rates of such components every two years by relying exclusively on technological improvements. Innovation in circuit and system design techniques would also be essential.
This is expected to lead to the integration of multiple silicon technologies on one chip and the integration of package and silicon technology to create Performance Systems on a Chip (P-SoC).
Robert Doering, a senior fellow in silicon technology development at Texas Instruments, said: "Each challenge is an opportunity for the semiconductor R&D community to add to the history of breakthrough achievements upon which the growth of our industry has been based."
And according to the SIA, as new generations of Dram chips start being introduced ever four years, MPUs and high end Asics will begin to set the pace in the industry.
For example, MPU gate lengths are expected to grow much faster than Dram cell pitch. As a result, by 2005, when the Dram half pitch is scheduled to hit 100 nanometers, MPU gate lengths should be 65 nm.
Last month, the SIA said it expected the processor market to grow by 15 per cent this year, fueled by the proliferation of chips used to drive communications and the Internet's infrastructure.
The organisation forecast that worldwide chip sales would top $144 billion in 1999 and jump 21 per cent to $174 billion in 2000, reaching a high of $234 billion in 2002.
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