Memory chip maker Micron is pushing flash solid state drives (SSDs) as the technology of choice for enterprise storage, yet does not expect magnetic media to go away anytime soon. The firm is also looking to new technologies such as 3D Nand flash in order to meet the density challenges of the future.
Micron, which last week started sampling its first 16nm flash devices, said there is growing demand for SSDs across all storage segments, whether enterprise or consumer, but does not see them replacing hard drives anytime soon.
Glen Hawk, Micron's vice president of Nand Solutions, told V3 that he believes there will always be a place for hard drives in the industry, just like there is still a legitimate need for tape storage.
"I think hard drives are certainly going to be around for a long time for the same reason. For certain storage applications, hard drives are going to remain the lower cost option," he said.
This may sound strange for a manufacturer of flash memory, but the storage industry is currently trying to work out where and how is the best way to use the high-speed memory technology most effectively.
"As people start to get really familiar with flash, the usage models are changing very quickly and we're trying to react quickly to figure out how to bring new products to market to deal with that," Hawk said.
This has led to an array of different solutions, with some enterprise vendors using a small amount of costly flash to cache lower-speed hard disks, while others are adopting all-flash arrays as storage Tier 1, or even using flash for a new Tier 0.
"They've not necessarily gone in and simply displaced all their hard drives, they've actually created a new tier in that hierarchy of memory, that's where flash has traditionally been inserted, but we believe it will start working closer and closer to the processor, and that's going to require new bus connections," Hawk said.
He pointed to some of the enterprise flash products that already use a direct PCI Express connection to the host system, as the Sata and SAS interfaces inherited from spinning hard drives are too much of a bottleneck.
But as new process technologies enable more and more bits to be packed into a memory chip, even the connections to the memory chip are becoming a problem, according to Hawk.
"One of the problems that we have is that while we're incredibly good at shrinking the memory cell size, one of the limitations we're running into now is that there is an I/O bottleneck within the chip. We're fundamentally limited by having just a few I/O pins to pass all this data through," he said.
One possible solution is to perform processing on data inside the memory chip itself, Hawk said, rather than shuffling it backwards and forwards between memory and processor.
"Why are we wasting energy moving that data out of the chip, just so a microprocessor can go operate on it, so why can't you do some of the processing inside of that memory? I do think that in the next few years, you will start to see some rudimentary levels of processing within the memory," he said.
However, he conceded that this is something that is only likely to develop over the long term, as it would need a radical change in computer architectures.
In the near term, the major "next revolution" for Nand flash will be 3D Nand, whereby the memory cells on a chip are stacked on top of each other vertically instead of spread out in a 2D grid.
Micron is just one company that is investigating this approach, which is needed because the gates that make up each memory chip have now shrunk to the point where they are approaching fundamental physical limits, according to Hawk.
"We're now dealing with a situation where the difference between states is in the order of 10 or 20 electrons, and they are very poorly behaved in small numbers, so we're reaching fundamental limits, but we can keep going for another couple of generations with the current high-k metal gate technology," he explained.
With the ability to expand into the third dimension, gates can be made larger while increasing density for a given size of chip.
"So you can increase the reliability, you can increase the performance, and it gives us an excellent path for continued scaling, because 3D Nand sort of resets the clock. It's a big costly transition to do this, but it will happen," Hawk said.
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