Advanced Micro Devices, Cyrix and IDT are veering off in very different market directions from each other - and Intel, it emerged at the Microprocessor Forum in San Jose this week.
However, industry watchers believe that diversity will be good for the sector, despite the added complexity, because it will allow room for processors and systems that are optimised for specific markets, such as low-price multimedia systems.
At the conference, Advanced Micro Devices (AMD) revealed the most ambitious and arguably the most risky processor roadmap because, unlike its x86-compatible rivals, it intends to compete with Intel in multiple segments of the PC market, including symmetrical multiprocessing (SMP) machines.
Its K7 processor, which is due to ship in the first half of 1999, will use a new bus design based on the Alpha EV6 bus technology that AMD licensed from Digital (now owned by Compaq), but the move marks a departure from Intel's current strategy and that of its clone-makers.
The K7 will debut in .25 micron and have clock speeds of 500 MHz or higher. It will feature three integer units and three multimedia execution units, and is designed to optimise clock speed. As a result, it will be aimed at processor-hungry applications running on workstations and servers.
Cyrix, meanwhile, is moving in a very different direction to its rival. The firm outlined plans for a new processor core codenamed Jalapeno, which will appear in its M3 chip initially.
This is expected to start sampling in the fourth quarter of 1999 and will start at clock speeds of about 600 MHz. It is expected to scale to ?well over? one GHz, Cyrix claimed, and will include a new memory controller to speed up memory access, 256 KB of level 2 cache and on-chip 3D graphics circuitry.
Jalapeno is intended to minimise memory latency, which, the company believes, is the main cause of current performance bottlenecks, but some parallel capabilities will be lost as a result.
The chip will also come with a relatively modest dual-issue design, two integer units and two floating point/MMX units.
IDT, on the other hand, is positioning its offering at the low-end of the market. Its current WinChip 2 is the smallest x86 processor available, which bears a direct relation to pricing. The company is currently also working on a ?from scratch? design for its WinChip 4, which will enter production in the second half of 1999.
While IDT has lagged behind its competitors on clock speed up till now, the new design will be optimised for 400-500 MHz performance, the company claimed.
The first version of the WinChip 4 will be built in 0.25 micron technology and will be based on Socket 7. But a subsequent 0.18 micron version, due in the first half of 2000, will be based on a different bus architecture, although IDT would not disclose details. The shrink to .18 micron will bring the WinChip 4 down to a 60 mm2 die size.
?I think this diversity is a good thing, though it certainly adds complexity to the industry?, says Michael Slater, principal analyst at MicroDesign Resources, which organises the Microprocessor Forum.
According to Slater, diversification will allow room for processors and systems that are optimised for specific markets, such as low-price multimedia systems or high-end workstations.
But internal chip architectures and bus interfaces are not the only things that are diversifying, however - so are instruction sets.
?We started out with the whole industry based on a 386 instruction set. ?But now, for the first time in the industry, there are extensions from other vendors," says Slater.
The first major enhancement to the 386 instruction set came in the form of Intel's MMX technology, which has since been adopted by other players, but both Cyrix and IDT have now implemented the 3DNow! Instruction set developed by AMD.
Next year, however, Intel will offer its own response to 3DNow! in the shape of a new set of instructions currently dubbed Katmai New Instructions (KNI) despite AMD's promises that it will continue support for 3DNow!
Despite all the diversification taking place, however, Slater also distinguishes some common trends. All chip manufacturers will move towards implementing on-chip level 2 caches to boost performance, he believes, with the exception of IDT, which has chosen a very large level 1 cache instead.
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