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Intel announces 14nm Knights Landing processor in Xeon Phi update

17 Jun 2013
Intel Knights Landing Xeon Phi processor

Intel will deliver a 14nm standalone CPU as the next generation of its Xeon Phi many integrated core (MIC) supercomputing platform. The firm disclosed details at the International Semiconductor Conference (ISC 2103) in Leipzig, where it also unveiled new 7100, 3100 and 5100 families of its current Xeon Phi Coprocessor lineup.

Codenamed Knights Landing, the next generation Xeon Phi will be produced on a 14nm process technology, according to Dr Rajeeb Hazra, vice president of Intel's data centre and connected systems group.

It is unclear whether this will be Intel's first 14nm chip, as the company declined to indicate an availability date for the product. An update of Intel's mainstream Core chips codenamed Broadwell was expected to debut on 14nm later this year, but recent press coverage has suggested this may be delayed until sometime in 2014.

However, Hazra did disclose that Knights Landing will be able to operate as a CPU in its own right, while the current Xeon Phi products are designed as PCI Express coprocessors that work in concert with standard Intel CPUs.

"The most significant aspect of where this takes innovation forward is that it is no longer simply a PCI Express coprocessor. It is also a standalone CPU," he said.

The reason for this move is that using a coprocessor to offload the processing burden is "unnatural" for programmers to code for, according to Hazra.

"They simply want the ability to take what they do on a single CPU today but have much more pervasive threading and parallelism and vectorisation going on. And that is what we will be doing in the next generation Xeon Phi processor," he added.

Knights Landing will also feature integrated on-package memory, in an attempt to boost performance by moving the memory as close as possible to the processor instead of using GDDR5 memory chips, as the current Xeon Phi coprocessors do.

Intel's presentation also demonstrated that future processors would integrate an on-chip fabric controller, pushing communications speeds from 10-20Gbps to over 100Gbps. However, Hazra also refused to be drawn on whether this would debut in Knights Landing.

Meanwhile, the 7100, 3100 and 5100 Xeon Phi families are shipping now, according to Intel, offering a "whole lineup of products to meet a spectrum of end-user needs".

The 7100 family is the highest performance Xeon Phi line at over 1.2 double-precision teraflops. It has 61 cores and 16GB GDDR5 with a bandwidth of 352GBps. A new value line, the 3100 family, is rated at over one double-precision teraflop with its 57 cores, and has 6GB GDDR5 with a bandwidth of 240GBps.

The 5100 family comes in a new high-density card form factor aimed at vendors looking to deliver a custom solution to customers, Intel said. This is also rated at over 1 double-precision teraflop but has 8GB GDDR5 with a bandwidth of over 300GBps.

Intel's Xeon Phi chips are based on a modified version of the x86 architecture found in its Xeon and Core chips, and the firm makes much of this commonality as an advantage for programmers.

Hazra said that Intel's "neo-heterogeneity" offers the ability to have "heterogeneous hardware in terms of multiple design points of the architecture", but that all can be coded for using a single programming model.

"With neo-heterogeneity, you can continue to leverage not only a vast amount of existing tools and software, but human capital and knowledge as well," he said.

The comment was intended as a swipe against the heterogeneous architecture espoused by Nvidia with its Cuda GPGPU technology for supercomputing, but also possibly aiming at AMD's Fusion architecture that combines CPU and GPU cores on a single chip.

AMD is also working towards giving programmers a single model for coding massively parallel applications, but its Heterogeneous System Architecture (HSA) approach is based on new tools such as the Open Computing Language (OpenCL) that is tailored for both CPU and GPU combinations.

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Daniel Robinson

Daniel Robinson is technology editor at V3, and has been working as a technology journalist for over two decades. Dan has served on a number of publications including PC Direct and enterprise news publication IT Week. Areas of coverage include desktops, laptops, smartphones, enterprise mobility, storage, networks, servers, microprocessors, virtualisation and cloud computing.

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