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Intel unveils Xeon E5 server chips for cloud computing and big data demands

by Daniel Robinson

06 Mar 2012

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Stacks in a datacentre

Intel has officially launched its Xeon E5-2600 series of server chips, which the firm said are designed to meet the rapidly increasing demands being placed on datacentres through the growth of cloud computing services and big data analytics tools.

The new Xeon E5 family supersedes the previous Xeon 5600 generation with the usual claims about increased processing performance, but this time Intel has also detailed changes designed to boost overall system throughput as well as energy efficiency, a sign of the changing demands of the IT world.

Although announced on Tuesday, the new chips have been widely anticipated, and have been in full production since Q3 2011, meaning that ample supplies of new servers based on the Xeon E5 chips should be ready from system vendors.

Dell unveiled its 12th generation Intel-based servers last week, while HP and IBM are among those expected to announce their own new systems today.

Graham Palmer, Intel managing director for the UK, said the company is trying to address the exploding volumes of data now being generated by cloud computing, the consumerisation of IT, and big data analytics applications.

"For every 600 new smartphones or 120 new tablets, another entire server is required just to service their needs," he said.

The Xeon E5 processors are 32nm chips based on Intel's Sandy Bridge architecture, and are designed for twin-socket systems with two, four, six, or eight processor cores per chip, which with Intel's Hyper-Threading technology, provides for up to 32 threads per server.

However, the new chips introduce several features designed to emphasise throughput, such as an extra DDR3 memory channel and a second QuickPath Interconnect (QPI) link. Each chip also supports up to 768GB of memory.

The Xeon E5 also introduces the latest PCI Express 3.0 bus for connecting I/O adapter devices, moving the controller from the motherboard chipset onto the processor itself to reduce latency.

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