SC11: Intel unveils Knight's Corner prototype for exascale supercomputing

SEATTLE: Intel unveiled the first prototype builds of its Knight's Corner many integrated cores (MIC) processor at the 2011 SuperComputing conference (SC11).

The first versions of the chip can operate at speeds of more than one teraflop, or one trillion floating point operations per second.

Dr Rajeeb Hazra, general manager of Intel's technical computing group, said the chips will arrive with the company's line of 22nm processors, expected to begin in 2012.

Intel declined to provide details on the clock speed of the Knight's Corner chips, but executives said the core count will be more than 50.

The MIC chips will combine with the Xeon E5 models to form the basis of an exascale supercomputing platform planned for delivery by 2018.

The release comes as companies are beginning to step up the race to build an exascale supercomputer. Some have suggested 2019 as an informal target date, but industry executives believe that programming challenges could delay the release of fully functional systems by several years.

While other hardware vendors are relying on a combination of CPU and GPU processors to power supercomputer platforms, Intel will retain a common programming platform for the Xeon and MIC chips.

This platform will allow organisations to run legacy platforms without the need to change the way they develop code significantly.

"While we will surprise you with performance, we will not surprise you with how easy it is," Hazra said. "Programming is how you have always done it, with results you may never have had before."

Hazra noted that the prototype hardware has arrived less than 15 years after Intel developed its first terabyte supercomputer – the 1997 ASCI Red Cluster – which required 72 cabinets and used 9,298 processing cores.