IDF: Intel sheds light on tri-gate transistor plans

Intel has highlighted the benefits of its upcoming 22nm tri-gate transistors as the company prepares to produce the first chips based on the platform.

Intel senior fellow Mark Bohr took to the stage at IDF to outline some of the benefits of the 3D transistors, which are scheduled to enter production in late 2011 and hit the market in 2012.

Tri-gate transistors wrap a gate electrode around a series of 'fins', allowing multiple gates to be used with each transistor, unlike traditional transistor designs which use a flat, planar design.

Bohr explained that this better insulates transistors against energy leaks, and allows transistors to be activated with a lower power threshold. The result is a transistor which requires less power to run and can switch between on and off states in less time.

"You can have improved performance, but you can also operate at a lower voltage. And when you operate at a lower voltage, you save active power," he said.

Intel has been developing the tri-gate technology since 2006, and believes that,  combined with strained silicon and hi-k metal gate technologies, it will allow CPU and system-on-a-chip (SoC) hardware to continue to develop at a consistent rate.

Bohr said that Intel is planning to release CPU and SoC hardware at the 22nm and 14nm processes. Fabricating 22nm chips using planar transistors is possible, Bohr said, but the technology falls short of Intel's goals for performance and energy efficiency.

"Planar transistors cannot provide expected performance and power improvements at 22nm. We realised that was not enough of an improvement. We realised we could do better," he said.