Boffins in a spin over next-gen transistors

This breaks with currently proposed 'spintronic' architectures, which rely on a charge transfer for information exchange and show significant interconnect problems.

Professor Eshaghian-Wilner, in conjunction with Khitun and Professor Wang, has developed three spin-wave bus-based designs that use spin waves to achieve the low-power device performance and improved scalability highly desired by industry chip manufacturers.

The first device developed by UCLA engineers is a reconfigurable mesh interconnected with spin-wave buses.

The architecture of the device requires the same number of switches and buses as standard reconfigurable meshes, but is capable of simultaneously transmitting multiple waves using different frequencies on each of the spin-wave buses, making the parallel architecture capable of very fast and fault-tolerant algorithms.

"This innovative design represents an original approach for nano-scale computational devices while preserving all the advantages of wave-based computing," said Professor Eshaghian-Wilner.

"We are tremendously excited about the future of this research. The designs demonstrate outstanding performance as interconnects for massively parallel integrated circuits."

Khitun added: "Over the past few years, scientists have studied a variety of methods for designing nano-scale computer architectures. Our collaborative approach using spin-wave buses is a novel one that we hope will lead to additional breakthroughs."