AMD and Intel enter chip alliance (300)

Intel seems unlikely to face investigation from the US Department of Justice after it emerged today it has persuaded former fierce competitor Advanced Micro Devices (AMD) to its case.

That comes in the face of a massive sale of Cyrix/IBM chips to large corporations and end-users in the present financial quarter leading up to Christmas. This threatens both Intel and AMD, because of higher performance and lower costs for businesses although both companies insist that the Cyrix platform is no use for games.

Three years ago, AMD accused Intel of trying to dominate the market and CEO Jerry Sanders III declared: "Only real men have fabs". Most thought that was a dig at Cyrix, which had to use IBM and SGS Thomson fabs to survive.

AMD has signed deals with chip giant Intel to cut out upstart Cyrix and other x.86 manufacturers, according to distributors. That also cuts out IBM from the microprocessor picture, according to sources at IBM, Cyrix, SGS Thomson, TI and UMC in Taiwan. Cyrix/IBM chips are fast outselling both Intel and AMD outside the Americas, the distributors claim.

Dave Frink, head of PR at AMD in Texas, agreed the enemy was without rather than within. He said: "We care because we compete with Intel. We are working with Intel but that does not mean we agree with them." He said AMD would not push the DoJ to make a case against Intel but denied that was because Intel and AMD were in bed together.

He said that socket seven compatibility, meaning AMD could plug in faster K5 and K6 chips was not a disadvantage for his company, despite its agreement to license MMX technology from Intel. That was not an issue, he claimed.

Frink said: "We care because we compete with Intel." He denied AMD and Intel were in bed but he refused to comment on the terms of the MMX agreement.

The issue is real because Far East companies, including Acer, Dutch companies like Tulip, and a mass of assemblers here in the UK claim they can make extra profit on the desktop, despite Cyrix' lack of floating point architecture.