Intel's 65nm chip will make laptops go further

Intel has built a fully functional 70Mb static random access memory (SRam) chip with more than half a billion transistors, using 65nanometer (nm) process technology.

SRam chips are often used as test vehicles for new manufacturing processes because their design is relatively straightforward.

Intel said the new process technology would give the company "the foundation" on which to deliver future multi-core processors and add virtualisation and security capabilities.

The new chip shows off the power reduction potential of the 65nm technology.

"We placed even greater emphasis on power reduction ideas and techniques for this generation versus the previous ones," said Mark Bohr, Intel's director of process architecture and integration.

"When you make transistors smaller and employ power savings, that helps all mobile devices because of the average power consumption and battery life."

Among the more notable power saving technologies is one called Sleep Transistors, which will cut off the power to large blocks of the SRam when they are not in use, eliminating a significant source of power consumption on a chip.

The company said Sleep Transistors would be especially beneficial for battery-powered devices, such as laptops.

Transistors will normally consume any power provided to them whether they need it or not. This phenomenon, better known as leakage, gets more problematic as both chips and electric currents get smaller.

In Intel's SRam chip, the Sleep Transistors result in a threefold reduction in leakage. The savings in actual processors will be less than that, Intel expects, depending on factors such as cache size.

Chip manufacturers have only recently shifted from a 130nm to a 90nm production process, with the first chip, Intel's 90nm Pentium 4, being launched last January.

The transition, however, has been painful. Intel had to delay the introduction of the 90nm Pentium 4 processor by three months.

Bohr predicted that the conversion to 65nm would be smoother. "It will be for the second time on 65nm. We took most of those risks at the 90nm node," he said.