The instruction set for the new 64-bit Merced processor has been unveiled by developers Intel and Hewlett-Packard. The idea is to get developers working on code before the chip ships in volume next year.

Merced is the codename of the first of a range of IA-64 processors. They are based on an architecture called EPIC, which stands for explicitly parallel instruction computing.

The 'explicit' refers to the fact that the processor can be given information to help it, for instance, fetch data before it is needed, or to know which instructions can be processed in parallel.

The developers claims this overcomes some of the shortcomings of RISC (reduced instruction set computing) architecture. But it is said to place more demands on the programmer and compiler. Internal resources include 128 integer registers, 128 floating point registers, 64 predicate registers, and support for MMXTM and stream SIMD extensions.

It has been optimised for video encoding, crytography and other tasks which are expected to fall on next-generation servers.

IA-64 chips will run legacy 32-bit apps using either a 32-bit or 64-bit operating system (see diagram). But it will run HP's PA-RISC code only by using an emulator.

Details are at www.hp.com/go/ia-64 and developer.intel.com/design/ia64/index.htm

- See next month's PCW for more details.